For synchronous communications applications, many modems utilize a digital signal processor coupled with an analog "front end" to implement the signal processing. One illustrative front end 100 is shown in FIG. 1. As shown, in the receive portion of this front end, the incoming quadrature amplitude modulated (QAM) line signal from 2-wire communications path 101 is coupled through hybrid 102 and sampled by analog-to-digital (A/D) converter 103. Echo canceller 104 subtracts the synthesized echo from the digital samples provided by converter 103 using the transmit symbols provided by transmitter 110. The echo-free samples are then converted back to an analog signal by digital-to-analog converter (D/A) 105, passed through low-pass filter 106 and supplied to A/D converter 107. Converter 107 provides digital samples to Hilbert filter 108 which outputs the real and imaginary passband components of each supplied sample. These real and imaginary components, respectively designated as I and Q, are coupled to conventional receiver 109 which outputs the received data and the received bit clock that is synchronized to a remote transmitter clock. In the transmit direction, transmitter 110 accepts the incoming data and the transmit bit clock and provides the transmit symbols to pulse shaping circuit 111. The pulse shaped output of circuit 111 is then converted into an analog signal by D/A converter 112. For proper operation of echo canceller 104, A/D converter 103, D/A converter 105 and D/A converter 112 are strobed by the transmit sample clock while A/D converter 107 is strobed by the receive sample clock. Each of these converters is disposed between a pair of low-pass filters (not shown). Transmit sample clock generator 113 generates the transmit sample clock which is frequency locked to an externally supplied clock signal. This externally supplied clock signal is normally the transmit bit clock used by transmitter 110. The transmit and receive sample clocks are those clock signals used to strobe the A/D and D/A converters and such clocks normally have a higher frequency than the symbol rate. The challenge in implementing front end 100 is to provide precision converters on a single integrated circuit with asynchronous transmit and receive clocks.
To reduce costs, more recently developed modems utilize the illustrative front end 200 shown in FIG. 2. Front end 200 utilizes some of the elements described in FIG. 1 and such elements provide the same function and are designated by the same reference numerals in FIG. 2. In addition, front end 200 also includes a codec 201. As shown, a codec 201 incorporates precision A/D and D/A converters, respectively designated as 202 and 203. As in FIG. 1 and in the drawing figures to be discussed, each of these converters is disposed between a pair of low-pass filters (not shown). In modems incorporating an echo canceller 104, the codec must be strobed by a common sample clock defined as the transmit sample clock. Moreover, in modems not incorporating an echo canceller, it is often advantageous to utilize a common sample clock to increase performance. For illustrative purposes, it is assumed that this sample clock has a nominal frequency of 7200 Hz. It should, of course, be understood that the present invention is not limited to a particular sample clock frequency and may be used with any sample clock frequency. D/A converter 202 is utilized within the transmitter portion of the modem to form samples of the signal to be transmitted through 2-wire communications path 101 to a remote location. Similarly, A/D portion 203 is utilized within the receiver portion of the modem to form samples of the signals received from the remote location via path 101.
To compensate for the fact that A/D converter 203 is not synchronized to the transmitter clock at the remote location, the output of this A/D converter is coupled to digital interpolator 204 after passing through echo canceller 104 and Hilbert filter 108. The circuitry within interpolator 204 is well-known. One illustrative interpolator is disclosed in U.S. Pat. No. 4,866,647 to C. W. Farrow, "Continuously Variable Digital Delay Circuit," issued Sep. 12, 1989, and in an ISCAS 1988 conference paper to C. W. Farrow entitled, "Continuously Variable Digital Delay Element." Both of these documents are hereby incorporated by reference. The digital interpolator alters the sample values it receives in response to a control signal on lead 208. Timing recovery circuit 205 generates this control signal using a predetermined one of the outputs of the Hilbert filter along with sine and cosine wave forms supplied by sine/cosine calculator 206. The control signal is representative of any asynchronism between the transmit sample clock and the remote transmitter clock. The effect of the interpolator, therefore, is to alter the timing phase of the common sample clock source and provide the samples which would have been formed had the common sample clock been synchronized to the transmitter clock at the remote location. Receiver 207 recovers the received data from the I and Q outputs of the digital interpolator. In addition, receiver 207 also generates the receive bit clock, which synchronizes the received data, using the control signal on lead 208. This receiver is identical to its counterpart in FIG. 1 except that the timing recovery function has been extracted from the receiver in FIG. 2 and is provided by timing recovery circuit 205.
With the use of a common sample clock, the transmitting and receive portions of a transceiver are not independent since the samples of the received signal are generated at the transmit sample clock rate. While this use of a common sample clock source works satisfactorily for many modem applications, there are situations where problems arise. One such application 300 is shown in FIG. 3 where data between digital terminal equipment (DTE) 301 and 302 are coupled through 2-wire communications paths 303 and 304 and serially connected modems 305, 306, 307 and 308. The pair of modems 306 and 307 are connected in tandem, i.e., their digital RS-232 interfaces are directly connected to one another. In such an interface, the designations RD, RC, SD and SC respectively designate a modem's receive data, receive bit clock, send data and send bit clock leads. For error-free synchronous operation, the transmit sample clock of modem 307 which is used to clock the signal coupled to path 304 must be synchronous with the receive bit clock in modem 306. Similarly, in the reverse direction, the transmit sample clock of modem 306, used to transmit signals toward path 303, must be synchronous with the receive bit clock in modem 307. Therefore, each transmitter in the tandem modem pair can be referred to as being clocked by an externally supplied transmit sample clock signal, i.e., a transmit sample clock signal controlled by the other modem's receive bit clock. If modems 306 and 307 incorporate the circuitry of FIG. 2, the A/D and D/A converters in codec 201 do not operate independently as both are clocked by the transmit sample clock. As a result, a feedback loop is formed wherein perturbations in the transmit sample clock of modem 306 affect the operation of the receive bit clock in this modem. In addition, the transmit sample clock of modem 307 is derived from the receive bit clock of modem 306 and, in turn, affects the receive bit clock of modem 307 from which the transmit sample clock of modem 306 is derived. This feedback loop causes instability which results in data errors and eventual loss of timing synchronization. A solution to this problem has heretofore not been found.